1. Field of the Invention
This invention relates to the field of computing systems and more particularly to a bus bridge including a buffer pool having a buffer storage location adapted to be configured as either a fetch buffer or a post buffer depending on the needs of the system.
2. Description of the Relevant Art
FIG. 1 is a block diagram of a conventional computer system 10 including a processing unit (CPU) 12, a CPU local bus 14 coupled to processing unit 12, and a first bridge 16. A system memory 18 and an external cache memory 19 are further shown coupled to first bridge 16. A first bus 20 is coupled to CPU local bus 14 through first bridge 16. In an exemplary embodiment, first bus 20 complies with, for example, the PCI bus protocol . A first peripheral device 22 is connected to first bridge 16 through first bus 20. First peripheral device 22 is exemplified by, for example, an SCSI hard disk controller or a high resolution graphics adapter.
Processing unit 12 is illustrative of, for example, an x86 processing unit, and CPU local bus 14 is exemplary of an x86-style local bus. The CPU local bus 14 typically includes a set of data lines D[31:0], a set of address lines A[31:0], and a set of control lines (not shown individually). Details regarding the various bus cycles and protocols of x86 CPU local bus 14 are described in a host of publications of the known prior art.
First bridge 16 provides a standard interface between CPU local bus 14 and first bus 20. As such, first bus bridge 16 orchestrates the transfer of data, address, and control signals between the two buses. First bridge 16 additionally provides an interface between CPU 12 and system memory 18, which is typically comprised of a relatively slow and dense memory device or devices such as an array of dynamic RAMS, as well as an interface between CPU 12 and external cache 19. External cache 19 is typically comprised of an array of higher speed but less dense (i.e. more costly) memory devices such as an array of static RAMs. The contents of recently accessed locations within system memory 18 are typically stored in external cache 19 (or in an internal cache within CPU 12) on the assumption that recently accessed memory locations are more likely to be accessed by CPU 12 than memory locations that have not been recently accessed. If CPU 12 issues a command to a memory location whose contents are currently stored in external cache 19, CPU 12 can typically access the contents of the location from external cache 19 faster than it could do so from system memory 18 thereby improving system performance. The capacity (in bytes) of system memory 18 is typically in the range of approximately 10.sup.6 to 10.sup.7 whereas the capacity of cache memory 19 is typically in the vicinity of 10 .sup.3 to 10 .sup.4 bytes. First bus 20 is a high performance peripheral bus such as a PCI bus that supports burst-mode data transfers and that includes multiplexed data/address lines. First peripheral device 28 is illustrative of, for example, any PCI compatible peripheral device such as a disk controller.
Bus bridges such as first bus bridge 16 facilitate the transfer of information between busses operating at different clock frequencies. To accomplish this task, bus bridges typically include buffers or storage locations for temporarily storing information in transit from one of the busses connected to the bridge to another bus connected to the bridge. These bus bridge buffers are typically classified as either "post" buffers or "fetch" buffers according to their function. Post buffers store information written by an initiating device connected to one side of a bridge and intended for a receiving device connected on the other side of the bridge. A common example of this type of sequence occurs when CPU 12 writes information to system memory 18. CPU obtains mastership of CPU local bus 14 and "posts" the information, comprising the data itself, the address of the storage location to which the information is destined, and a signal that alerts first bridge 16 to the presence of the information on the CPU local bus 14. When first bridge 16 is ready to receive the posted information, first bridge 16 will obtain mastership of the CPU local bus in response to the signal sent by CPU 12 and, once it has obtained mastership of the bus, typically store the address and data into an internal post buffer. After the information has been stored, first bridge 16 releases mastership of the CPU local bus 14. Eventually, first bridge 16 will transfer the information from the storage buffer to system memory 18 thereby freeing up the post buffer for receiving additional information.
Fetching or pre-fetching occurs when a bus bridge 16 determines that there is a likelihood that a device on one of the system busses may require the contents of a given storage location. In one common example, first bridge 16 may predict that CPU 12 will soon require the contents of a particular memory location. Such a prediction is most often made when, for example, CPU 12 requests the contents of an immediately preceding storage location within system memory 18. Because is reasonable to suspect that if CPU 12 requires the contents of location 0.times.N (where N is a hexadecimal representation of the storage location address) during the execution of a particular instruction, it will shortly require the contents of storage location 0.times.N+1, first bridge 16 may be configured to speculatively retrieve the contents of one or more storage locations whenever first bridge 16 determines that a requesting device has recently retrieved information from an adjacent or neighboring storage location. As will be appreciated to those skilled in the art of computing systems architecture, information retrieved in this fashioned is said to be "speculatively" fetched or pre-fetched because it is not a certainty that any of the system devices will require the pre-fetched information. In any event, the pre-fetched information is stored within a pre-fetch buffer or storage location of first bridge 16. If the pre-fetched information is ultimately required by a requesting device, system performance is improved because less time is required to deliver the information from first bridge 16 than from system memory 18.
Thus, the post and fetch buffers of conventional bus bridges are segregated in function. The available storage buffers are allocated between post buffers and fetch buffers in the hardware of the bus bridge. If the execution of a particular piece of code results in a disproportionate usage of either the post buffers or the fetch buffers, the bus bridge is incapable of accommodating the disproportionate demands by varying the number of buffers for reads and writes. It would therefore be desirable to achieve a bus bridge capable of adjusting the allocation of storage buffers as post buffers or fetch buffers according to the prevailing demands of the computing system.